1. Field of the Invention
The present invention relates to technology for signal transmission between devices, such as a processor and a memory (between digital circuits formed by CMOS, for example, or between their functional blocks), and more particularly to technology for high-speed bus transmission among a plurality of devices connected to the same transmission line.
2. Description of Related Art
Among technologies for high-speed transmission between digital circuits formed with semiconductor integrated circuit devices, there is technology related to low-amplitude bus interfaces. Data output drivers used in the bus interface circuits are broadly divided into the open drain type circuits, a representative example of which is the GTL (Gunning Transceiver Logic) circuit, and the push-pull type circuits, representative examples of which are the CTT (Center Tapped Termination) interface circuit and the SSTL (Stub Series Terminated Logic) interface circuit. In data input receivers, the comparator type is generally used which compares input data with a reference voltage (Vref). The above-mentioned low-amplitude bus interfaces are described in detail in Nikkei Electronics, Sep. 27, 1993 issue (No.591) pp. 269-290, published by Nikkei BP.
With the progressive speedup of semiconductor integrated circuits in recent years, the rise time and the fall time of the leading and trailing edges of signal waveforms are decreasing, with the result that the waveform distortion due to mismatch of impedances is becoming too large to disregard. For this reason, as technology for eliminating the mismatch of impedances, the so-called matched termination method has been proposed, which terminates each end of the bus with a resistance equal to the bus line impedance.
FIG. 2 is a schematic block diagram of a bus system to which the conventional matched termination method is applied.
Reference numeral 50 denotes a main line of the bus, 51a to 51e denote stub lines of the bus, 52a to 52e denote drivers, 53a to 53e denote receivers, 54a to 54e denote modules, 55 denotes terminating resistors (Rtt) and 56 denotes the terminal voltages (Vtt). Reference numerals 57a to 57e denote branch points (connection points) of the stub lines 51a to 51e from the main line 50.
In the bus system in FIG. 2, the drivers 52a to 52e and the receivers 53a to 53e are arranged in pairs, and those pairs are respectively contained in a plurality of modules 54a to 54e, and connected through the stub lines 51a to 51e to the main line 50. The drivers 52a to 52e and their corresponding receivers 53a to 53e form the bus interface circuits of modules, each containing a driver and a receiver.
Though not illustrated, a logic circuit (LSI) for data transfer through the bus interface circuit is included in each module. Each bus interface circuit may be fabricated together with a logic LSI in the same chip or they may be fabricated separately.
Each end of the main line 50 is connected to a terminating resistor (Rtt) 55 that is connected to a terminal end voltage source (Vtt) 56, by which matched termination is obtained.
As described above, in the conventional bus system, the bus interface circuits (receivers/drivers) are connected through the stub lines to one main line.
In the transfer of data in such a bus system, the time of signal propagation varies with the position of the modules (more specifically, the position of the bus interface circuits) connected to the bus.
For example, when data is transferred from the driver 52d to the receiver 53e, a data signal goes along the stub line 51d, passes through the branch point 57d to the branch point 57e of the main line 50, and through the stub line 51e, and reaches the receiver 53e. On the other hand, when data is transferred from the driver 52a to the receiver 53e, a data signal travels along the stub line 51a, through the branch point 57a to the branch point 57e of the main line 50, and through the stub line 51e, and reaches the receiver 53e. In other words, if the data propagation time is compared between a case where data is transferred from the driver 52a to the receiver 53e and a case where data is transferred from the driver 52d to the receiver 53e, the propagation time in the former case is delayed by a period of time corresponding to a length of wiring between the branch points 52a and 57d of the main line 50.
The differences in propagation time among the modules at different positions become greater as the number of modules (more specifically, the number of the bus interface circuits) connected to the bus increases. The reason for this is that the wiring length of the main line becomes longer as the number of modules increases.
As the number of modules connected to the bus increases, the number of stub lines required to connect the modules to the main line increases, and accordingly the total capacitance of the stub lines increases, so that the effective velocity of propagation decreases.
In other words, the effective propagation velocity Vpxe2x80x2 of a signal, which propagates on the main line to which the stub lines are connected, decreases according to the amount of increase in the capacitance of the stub lines connected to the main line as compared with the propagation velocity Vp when there is only the main line (without the stub lines). The relational equation is shown below.
Vpxe2x80x2=Vp/(1+xcex94C/Co)xc2xdxe2x80x83xe2x80x83(Eq.1)
Where xcex94C is the capacitance of the stub lines as viewed from the main line, and includes the input capacitance of the modules connected to the stub lines. Co denotes the line capacitance between the branch points of the main line 50 on which a data signal propagates. From this equation, it is understood that the more stub capacitance xcex94C increases, the more effective propagation velocity Vpxe2x80x2 decreases.
In the conventional bus system, the above-mentioned problems hinder the attempts to achieve high-speed signal transmission.
The present invention has been made to solve those problems, and has as its object to speed up the bus system and improve the system performance.
Specifically, the propagation time among the modules is shortened to thereby speed up the bus system and improve the system performance.
The noise of the propagating signal waveform between the modules is reduced to accelerate the speed of the bus system and improve the system performance.
In order to solve the above problems, according to a first embodiment of the present invention, there is provided a bus system for data transfer among a plurality of interface circuits, which comprises:
at least two main lines connected together at opposite ends; and
a plurality of stub lines provided on a one-to-one correspondence with the above-mentioned plurality of interface circuits and connecting the corresponding interface circuits to one of the above-mentioned at least two main lines.
The first embodiment of the present invention, due to the above-mentioned structure, has the following advantages over the conventional bus system using one main line.
(1) If the lengths of wire between the branch points of the stub lines from the main line are set to be equal, the length of the main line on which data travels when it propagates between the mutually remotest interface circuits can be reduced to almost less than a half of the distance it would otherwise have to travel. Therefore, the data propagation time between the mutually remotest interface circuits can be made shorter. Furthermore, the differences in data propagation time between the interface circuits can be reduced.
(2) In the propagation of data between the mutually remotest interface circuits, the number of branch points of the stub lines from the main line that the data travels can be reduced. In other words, it is possible to reduce the number (capacitance) of the stub lines that affect the data waveform and the data propagation time. Let us discuss a concrete example. It can occur that the wiring length of the main line between the branch points of the stub lines from the main line must become longer than in the prior art for the structural reason of a circuit board that uses the bus system according to the present invention. In the case mentioned above, more specifically, even when the modules are mounted on one surface of the circuit board, the data propagation time between the mutually remotest interface circuits can be shortened. Furthermore, the differences in the data propagation time between the interface circuits can be reduced.
Thus, the speedup of the bus line can be achieved, which contributes to the improvement in the system performance.
According to a second embodiment of the present invention, there is provided a bus system for data transfer between a plurality of interface circuits, which comprises:
a main line in a ring form;
an interface circuit for data transmission, connected through a stub line to the main line;
a resistor having a constant voltage applied, and connected at the electrically remotest end position from the above-mentioned interface circuit for data transmission on the main line; and
a plurality of interface circuits for data reception, respectively connected to the main line through stub lines.
The second embodiment of the present invention, by its configuration mentioned above, achieves the same effects as in the first embodiment. Data transmitted from the data-transmitting interface circuit propagates clockwise and counterclockwise on the main line, and data on the CW route and data on the CCW route almost simultaneously reach the connection point of the resistor with the main line. By setting a value of the resistor so that a signal wave passing the connection point and a reflected wave produced at the connection point cancel each other out, perfect termination can be achieved.
In the second embodiment, a driver with an output impedance almost equal to the resistor may be used in place of the resistor.
According to a third embodiment of the present invention, there is provided a bus system for data transfer among a plurality of interface circuits, comprising:
a main line formed in a ring;
a plurality of stub lines connecting the above-mentioned plurality of interface circuits to the above-mentioned main line; and
a plurality of resistors having a constant voltage applied, and provided on a one-to-one correspondence with the above-mentioned plurality of interface circuits, wherein each of the above-mentioned resistors is connected to the main line through a switch at the electrically remotest end position from the corresponding interface circuit, and wherein each of the above-mentioned interface circuits has means for outputting a control signal to turn on the switch connected to the corresponding resistor before sending data onto the main line.
The third embodiment, by the above-mentioned arrangement, achieves the same effects as in the first and the second embodiments. Moreover, the third embodiment can terminate the bus with a perfect termination when data is output from any interface circuit.
In the third embodiment, a driver which conducts in response to a control signal can be used in place of the resistor connected through the switch.